39K30 Datasheet, PDF (12/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Table 6 describes the valid phase shift options that can be
used with or without an external feedback.
Table 7 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift
applies to the VCO output and not to the divided output.
For more details on the architecture and operation of this PLL
please refer to the application note entitled “Delta39K PLL and
Clock Tree”.
Table 4. Valid PLL Multiply and Divide Options—without External Feedback
Input Frequency
(GCLK[0])
f_PLLI (MHz)
DC–12.5
100–133
50–133
33.3–88.7
25–66
20–53.2
16.6–44.3
12.5–33
12.5–16.625
Valid Multiply Options
VCO Output
Value Frequency (MHz)
N/A
N/A
1
100–133
2
100–266
3
100–266
4
100–266
5
100–266
6
100–266
8
100–266
16
200–266
Value
N/A
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
Valid Divide Options
Output Frequency (INTCLK[3:0])
f_PLLO (MHz)
DC–12.5
6.25–133
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
Off-chip Clock
Frequency
DC–6.25
3.125–66
3.125–133
3.1–266
3.125–133
3.1–133
3.1–133
3.125–133
3.125–133
Table 5. Valid PLL Multiply and Divide Options—With External Feedback
Input (GCLK) Frequency
f_PLLI (MHz)
50–133
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
Valid Multiply Options
VCO Output
Value Frequency (MHz)
1
100–266
1
100–266
1
100–266
1
100–266
1
125–266
1
150–266
1
200–266
Valid Divide Options
Output (INTCLK) Frequency Off-chip Clock
Value
f_PLLO (MHz)
Frequency
1 100–266
50–133
2 50–133
25–66.5
3 33.33–88.66
16.67–44.33
4 25–66.5
12.5–33.25
5 25–53.2
12.5–26.6
6 25–44.34
12.5–22.17
8 25–33.25
12.5–16.63
Table 6. Recommended PLL Phase Shift Options
Without External Feedback
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
With External Feedback
0°
Table 7. Timing of Clock Phases for all Divide Options for a V_CO Output Frequency of 250 MHz
Divide Period
0° 45° 90°
Factor (ns) Duty Cycle% (ns) (ns) (ns)
135°
(ns)
180°
(ns)
225°
(ns)
1
4
40–60
0
0.5 1.0
1.5
2.0
2.5
2
8
50
0
0.5 1.0
1.5
2.0
2.5
3
12
33–67
0
0.5 1.0
1.5
2.0
2.5
4
16
50
0
0.5 1.0
1.5
2.0
2.5
5
20
40–60
0
0.5 1.0
1.5
2.0
2.5
6
24
50
0
0.5 1.0
1.5
2.0
2.5
8
32
50
0
0.5 1.0
1.5
2.0
2.5
16
64
50
0
0.5 1.0
1.5
2.0
2.5
270°
(ns)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
315°
(ns)
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
Document #: 38-03039 Rev. *H
Page 12 of 86