39K30 Datasheet, PDF (19/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Descriptions Over the Operating Range^[13] (continued)
Parameter
Description
t_CKIN
Delay from the clock pin to the input of the clock driver
t_IOREGPIN Delay from the I/O pin to the input of the I/O register
PLL Parameters
t_MCCJ
Maximum cycle to cycle jitter time
t_DWSA
PLL zero phase delay with clock tree deskewed
t_DWOSA PLL zero phase delay without clock tree deskewed
t_LOCK
Lock time for the PLL
t_INDUTY
Input duty cycle
f_PLLI
Input frequency of the PLL
f_PLLO
Output frequency of the PLL
f_PLLVCO PLL VCO frequency of operation
P_SAPLLI Percentage modulation allowed (spread awareness) on the PLL input clock
f_MPLLI
Frequency of modulation allowed on PLL input clock. This specifies how fast the f_PLLI sweeps between f_PLLI*
(1–P_SAPLLI/100) and f_PLLI* (1+ P_SAPLLI/100)
JTAG Parameters
t_JCKH
t_JCKL
t_JCP
t_JSU
t_JH
t_JCO
t_JXZ
t_JZX
TCLK HIGH time
TCLK LOW time
TCLK clock period
JTAG port set-up time (TDI/TMS inputs)
JTAG port hold time (TDI/TMS inputs)
JTAG port clock to output time (TDO)
JTAG port valid output to high impedance (TDO)
JTAG port high impedance to valid output (TDO)
Cluster Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Asynchronous Mode Parameters
t_CLMAA
Cluster memory access time. Delay from address change to Read data out
t_CLMPWE
Write Enable pulse width
t_CLMSA
Address set-up to the beginning of Write Enable with both signals from the same I/O block
t_CLMHA
Address hold after the end of Write Enable with both signals from the same I/O block
t_CLMSD
Data set-up to the end of Write Enable
t_CLMHD
Data hold after the end of Write Enable
Synchronous Mode Parameters
t_CLMCYC1
Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
t_CLMCYC2
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
t_CLMS
t_CLMH
t_CLMDV1
t_CLMDV2
t_CLMMACS1
t_CLMMACS2
t_MACCLMS1
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
Document #: 38-03039 Rev. *H
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