39K30 Datasheet, PDF (18/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Descriptions Over the Operating Range^[13]
Parameter
Description
Combinatorial Mode Parameters
t_PD
Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the
horizontal or vertical channel associated with that cluster
t_EA
Global control to output enable
t_ER
Global control to output disable
t_PRR
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel
associated with the cluster the macrocell is in
t_PRO
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated
with the cluster that the macrocell is in to any pin output on those same channels
t_PRW
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest
cluster on the horizontal or vertical channel the pin is associated with
Synchronous Clocking Parameters
t_MCS
Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
t_MCH
Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
t_MCCO
Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the
cluster that macrocell is in
t_IOS
t_IOH
t_IOCO
t_SCS
t_SCS2
t_ICS
t_OCS
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Clock to output of an I/O cell register to the output pin associated with that register
Macrocell clock to macrocell clock through array logic within the same cluster
Macrocell clock to macrocell clock through array logic in different clusters on the same channel
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the
macrocell is in
t_CHZ
t_CLZ
f_MAX
f_MAX2
Clock to output disable (high-impedance)
Clock to output enable (low-impedance)
Maximum frequency with internal feedback—within the same cluster
Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or vertical
channel
Product Term Clock
t_MCSPT
Set-up time for macrocell used as input register, from input to product term clock
t_MCHPT
Hold time of macrocell used as an input register
t_MCCOPT Product term clock to output delay from input pin
t_SCS2PT Register to register delay through array logic in different clusters on the same channel using a product term clock
Channel Interconnect Parameters
t_CHSW
Adder for a signal to switch from a horizontal to vertical channel and vice-versa
t_CL2CL
Cluster-to-cluster delay adder (through channels and channel PIM)
Miscellaneous Delays
t_CPLD
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter
can be added to the t_PD and t_SCS parameters for each extra pass through the AND/OR array required by a given
signal path
t_MCCD
Adder for carry chain logic per macrocell
t_IOD
Delay from the input of the output buffer to the I/O pin
t_IOIN
Delay from the I/O pin to the input of the channel buffer
Note:
13. Add t_CHSW to signals making a horizontal to vertical channel switch or vice-versa.
Document #: 38-03039 Rev. *H
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