39K30 Datasheet, PDF(46/86 Page) Cypress Semiconductor

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39K30 Datasheet, PDF (46/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

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Delta39Kâ¢ ISRâ¢

CPLD Family

Table 8. Pin Definition Table

Pin Name

Reconfig

TCLK

TDI

TDO

TMS

VCC

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCJTAG

VCCCNFG

VCCPLL[18]

VCCPRG

Config_Done

CCLK

CCE

Data

Reset

Function

Input

Output

Input

Power

Output

Input

Output

Description

Pin to start configuration of Delta39K

JTAG Test Clock

JTAG Test Data In

JTAG Test Data Out

JTAG Test Mode Select

Operating Voltage

VCC for I/O bank 0

VCC for I/O bank 1

VCC for I/O bank 2

VCC for I/O bank 3

VCC for I/O bank 4

VCC for I/O bank 5

VCC for I/O bank 6

VCC for I/O bank 7

VCC for JTAG pins

VCC for Configuration port

VCC for PLL

VCC for programming the Self-Bootâ¢ solution embedded boot PROM

Flag indicating that configuration is complete

Configuration Clock for serial interface with the external boot PROM

Chip select for the external boot PROM (active low)

Pin to receive configuration data from the external boot PROM

Reset signal to interface with the external boot PROM

Table 9. Mode Select (MSEL) Pin Connectivity Table

GND

VCCCNFG

Delta39K - Self-Bootâ¢ Solution

Delta39K - with external boot PROM

Table 10. I/O Banks for Global Clock and Global Control

Pins (in all densities and packages)

Bank

Number

GCLK[0]

GCTL[0]

GCLK[1]

GCTL[1]

GCLK[2]

GCTL[2]

GCLK[3]

GCTL[3]

Table 11. 208 EQFP/PQFP Pin Table

CY39030

CY39050

CY39100

CY39165

CY39200

GCTL0

GND

GCLK0

GND

IO0

IO/VREF0

IO0

VCCIO0

Note:

18. The PLL is available in Delta39K âVâ devices (2.5V/3.3V) and not in Delta39K âZâ devices (1.8V). In Delta39K âZâ devices, connect VCCPLL to VCC.

Document #: 38-03039 Rev. *H

Page 46 of 86

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