39K30 Datasheet, PDF (17/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Capacitance
Parameter
Description
C_I/O
C_CLK
C_PCI
Input/Output Capacitance
Clock Signal Capacitance
PCI-compliant^[9] Capacitance
DC Characteristics (I/O)^[10]
Test Conditions
V_in = V_CCIO @ f = 1 MHz 25°C
V_in = V_CCIO @ f = 1 MHz 25°C
V_in = V_CCIO @ f = 1 MHz 25°C
Min. Max.
Unit
10
pF
5
12
pF
8
pF
V_REF V_CCIO
I/O Standards (V) (V)
LVTTL –2 mA N/A 3.3
LVTTL –4 mA
3.3
LVTTL –6 mA
3.3
LVTTL –8 mA
3.3
LVTTL –12 mA
3.3
LVTTL –16 mA
3.3
LVTTL –24 mA
3.3
LVCMOS
3.3
LVCMOS3
3.0
2.5
LVCMOS2
V_OH (V)
@ I_OH =
–2 mA
–4 mA
–6 mA
–8 mA
–12 mA
–16 mA
–24 mA
–0.1 mA
–0.1 mA
–0.1 mA
–1.0 mA
V_OH (min.)
2.4
2.4
2.4
2.4
2.4
2.4
2.4
V_CCIO – 0.2V
V_CCIO – 0.2V
2.1
2.0
V_OL (V)
V_OL
@ I_OL = (max.)
2 mA
0.4
4 mA
0.4
6 mA
0.4
8 mA
0.4
12 mA
0.4
16 mA
0.4
24 mA
0.4
0.1 mA 0.2
0.1 mA 0.2
0.1 mA 0.2
1.0 mA 0.4
V_IH (V)
V_IL (V)
Min.
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
1.7V
Max. Min.
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
V_CCIO + 0.3 –0.3V
Max.
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.7V
–2.0 mA
1.7
2.0 mA 0.7
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
1.0
1.5
1.5
1.25
1.25
0.75
0.75
0.9
0.9
1.8 –2 mA V_CCIO – 0.45V 2.0 mA 0.45 0.65V_CCIO V_CCIO + 0.3 –0.3V 0.35V_CCIO
3.3 –0.5 mA
[11]
0.9V_CCIO
1.5 mA 0.1V_CCIO 0.5V_CCIO V_CCIO + 0.5 –0.5V 0.3V_CCIO
36 mA^[12] 0.6
V_REF + 0.2
V_REF – 0.2
3.3 –8 mA V_CCIO – 1.1V 8 mA
0.7 V_REF + 0.2 V_CCIO + 0.3 –0.3V V_REF – 0.2
3.3 –16 mA V_CCIO – 0.9V 16 mA
0.5 V_REF + 0.2 V_CCIO + 0.3 –0.3V V_REF – 0.2
2.5 –7.6 mA V_CCIO – 0.62V 7.6 mA 0.54 V_REF + 0.18 V_CCIO + 0.3 –0.3V V_REF – 0.18
2.5 –15.2 mA V_CCIO – 0.43V 15.2 mA 0.35 V_REF + 0.18 V_CCIO + 0.3 –0.3V V_REF – 0.18
1.5 –8 mA V_CCIO – 0.4V 8 mA
0.4 V_REF + 0.1 V_CCIO + 0.3 –0.3V V_REF – 0.1
1.5 –16 mA V_CCIO – 0.4V 16 mA
0.4 V_REF + 0.1 V_CCIO + 0.3 –0.3V V_REF – 0.1
1.5 –8 mA V_CCIO – 0.4V 24 mA
0.4 V_REF + 0.1 V_CCIO + 0.3 –0.3V V_REF – 0.1
1.5 –8 mA V_CCIO – 0.4V 48 mA
0.4 V_REF + 0.1 V_CCIO + 0.3 –0.3V V_REF – 0.1
Configuration Parameters
Parameter
t_RECONFIG
Description
Reconfig pin LOW time before it goes HIGH
Min.
Unit
200
ns
Power-up Sequence Requirements
• Upon power-up, all the outputs remain three-stated until all
the V_CC pins have powered-up to the nominal voltage and
the part has completed configuration.
• The part will not start configuration until V_CC, V_CCIO,
V_CCJTAG, V_CCCNFG, V_CCPLL and V_CCPRG have reached
nominal voltage.
• V_CC pins can be powered up in any order. This includes
V_CC, V_CCIO, V_CCJTAG, V_CCCNFG, V_CCPLL and V_CCPRG.
• All V_CCIOs on a bank should be tied to the same potential
and powered up together.
• All V_CCIOs (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
• Maximum ramp time for all V_CCs should be 0V to nominal
voltage in 100 ms.
Notes:
9. PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 45, identify all the I/O pins in
a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf.
10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of V_CCIO and GND pins being used. Please refer
to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details.
• The source current limit per I/O bank per Vccio pin is 165 mA.
• The sink current limit per I/O bank per GND pin is 230 mA.
11. See “Power-up Sequence Requirements” below for V_CCIO requirement.
12. 25W resistor terminated to termination voltage of 1.5V.
Document #: 38-03039 Rev. *H
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