39K30 Datasheet, PDF (10/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
From
Output PIM
To Routing
Channel
Input
Mux
C
OE Mux
3
C
Register Input
Mux
Registered OE
Mux
DQ
C
RES
C
Output Mux
Register Enable
Mux
3
C
Clock Mux
Clock
Polarity
Mux
DQ
E
RES
Bus
Hold
I/O
C
C
Slew
Rate
Control
C
2
C
C
Register Reset
Mux
3
C
Figure 8. Block Diagram of I/O Cell
I/O Signals
There are four dedicated inputs (GCTL[3:0]) that are used as
Global I/O Control Signals available to every I/O cell. These
global I/O control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8. These global control signals, driven from four
dedicated pins, can only be used as active-high signals and
are available only to the I/O cells thereby implementing fast
resets, register and output enables.
In addition, there are six OCC signals available to each I/O
cell. These control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8. Unlike global control signals, these OCC signal can
be driven from internal logic or and I/O pin.
One of the four global clocks can be selected as the clock for
the I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock
Slew Rate Control
The output buffer has a slew rate control option. This allows
the output buffer to slew at a fast rate (3 V/ns) or a slow rate
(1 V/ns). All I/Os default to fast slew rate. For designs
concerned with meeting FCC emissions standards the slow
edge provides for lower system noise. For designs requiring
very high performance the fast edge rate provides maximum
system performance.
Table 3.
I/O
Standard
LVTTL
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
I/O Standards
V_REF (V)
Min. Max.
N/A
0.9
1.1
1.3
1.7
1.3
1.7
1.15 1.35
1.15 1.35
0.68
0.9
0.68
0.9
0.68
0.9
0.68
0.9
V_CCIO
3.3V
3.3V
3.0V
2.5V
1.8V
3.3V
N/A
3.3V
3.3V
2.5V
2.5V
1.5V
1.5V
1.5V
1.5V
Termination
Voltage (V_TT)
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
1.25
1.25
0.75
0.75
1.5
1.5
Document #: 38-03039 Rev. *H
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