39K30 Datasheet, PDF (34/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Channel Memory Synchronous FIFO Empty/Write Timing
PORT B CLOCK
t_CHMFS
t_CHMFH
t_CHMCLK
WRITE ENABLE
Delta39K™ ISR™
CPLD Family
REGISTERED
INPUT
EMPTY FLAG
(Active LOW)
PORT A CLOCK
READ ENABLE
RE
REGISTERED
OUTPUT
D_n+1
t_CHMSKEW2 t_CHMFO
t_CHMFO
t_CHMFRDV
Document #: 38-03039 Rev. *H
Page 34 of 86