39K30 Datasheet, PDF (22/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Values Over the Operating Range (continued)
Parameter
t_INDUTY
f_PLLO[14]
f_PLLI[14]
f_PLLVCO
P_SAPLLI
f_MPLLI
JTAG Parameters
t_JCKH
t_JCKL
t_JCP
t_JSU
t_JH
t_JCO
t_JXZ
t_JZX
233
Min. Max.
40
60
6.2
266
12.5 133
100
266
–0.3 +0.3
50
25
25
50
10
10
20
20
20
200
Min. Max.
40
60
6.2
266
12.5 133
100 266
–0.3 +0.3
50
25
25
50
10
10
20
20
20
181
Min. Max.
40
60
6.2
266
12.5 133
100 266
–0.3 +0.3
50
25
25
50
10
10
20
20
20
125
Min. Max.
40
60
6.2
200
12.5
100
100
266
–0.3 +0.3
50
25
25
50
10
10
20
20
20
83
Min. Max.
40
60
6.2
200
12.5 100
100
266
–0.3 +0.3
50
25
25
50
10
10
20
20
20
Unit
%
MHz
MHz
MHz
%
KHz
ns
ns
ns
ns
ns
ns
ns
ns
Input and Output Standard Timing Delay
Adjustments
All the timing specifications in this data sheet are specified
based on LVCMOS compliant inputs and outputs (fast slew
rates).^[15] Apply following adjustments if the inputs and outputs
are configured to operate at other standards.
Output Delay Adjustments
Fast Slew Rate
Slow Slew Rate
(additional delay to fast slew rate)
Input Delay Adjustments
I/O Standard
LVTTL – 2 mA
t_IOD
t_EA
2.75
0
t_ER
0
t_IODSLOW
2.6
t_EASLOW t_ERSLOW t_IOIN
2.0
2.0
0
t_CKIN
0
t_IOREGPIN
0
LVTTL – 4 mA
1.8
0
0
2.5
2.0
2.0
0
0
0
LVTTL – 6 mA
1.8
0
0
2.5
2.0
2.0
0
0
0
LVTTL – 8 mA
1.2
0
0
2.4
2.0
2.0
0
0
0
LVTTL – 12 mA
0.6
0
0
2.3
2.0
2.0
0
0
0
LVTTL – 16 mA
0.16
0
0
2.0
2.0
2.0
0
0
0
LVTTL – 24 mA
0
0
0
1.6
2.0
2.0
0
0
0
LVCMOS
0
0
0
2.0
2.0
2.0
0
0
0
LVCMOS3
0.14 0.05
0
2.0
2.0
2.0
0.1
0.1
0.2
LVCMOS2
0.41
0.1
0
2.0
2.0
2.0
0.2
0.2
0.4
LVCMOS18
1.6
0.7
0.1
2.1
2.0
2.0
0.5
0.4
0.3
3.3V PCI
GTL+
–0.14
0
0
2.0
0.02^[16] 0.6^[16] 0.9^[16]
2.0
2.0
2.0
0
0
0
2.0
2.0
0.5
0.4
0.2
SSTL3 I
–0.15 0.3
0.1
2.0
2.0
2.0
0.5
0.3
0.3
SSTL3 II
–0.4
0.2
0
2.0
2.0
2.0
0.5
0.3
0.3
Notes:
14. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operation.
15. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.
16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
Document #: 38-03039 Rev. *H
Page 22 of 86