39K30 Datasheet, PDF (27/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Cluster Memory Asynchronous Timing
ADDRESS (AT
THE CLUSTER
INPUT)
READ
WRITE ENABLE
INPUT
OUTPUT
t_CLMCLAA
Cluster Memory Asynchronous Timing 2
ADDRESS (AT THE
I/O PIN)
READ
WRITE ENABLE
INPUT
OUTPUT
t_CLMAA
Delta39K™ ISR™
CPLD Family
WRITE
READ
t_CLMPWE
t_CLMCLAA
WRITE
READ
t_CLMSA
t_CLMHA
t_CLMPWE
t_CLMSD
t_CLMHD
t_CLMAA
Document #: 38-03039 Rev. *H
Page 27 of 86