39K30 Datasheet, PDF (25/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Registered Output with Synchronous Clocking (Macrocell)
INPUT
t_MCS
t_MCH
SYNCHRONOUS
CLOCK
REGISTERED
OUTPUT
Registered Input in I/O Cell
DATA
INPUT
INPUT REGISTER
CLOCK
REGISTERED
OUTPUT
Clock to Clock
INPUT REGISTER
CLOCK
MACROCELL
REGISTER CLOCK
PT Clock to PT Clock
DATA
INPUT
PT CLOCK
t_MCCO
t_IOS
t_IOH
t_IOCO
t_ICS
t_MCSPT
Delta39K™ ISR™
CPLD Family
t_SCS
t_SCS2PT
Document #: 38-03039 Rev. *H
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