39K30 Datasheet, PDF (36/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Channel Memory Synchronous FIFO Programmable Flag Timing
PORT B CLOCK
WRITE ENABLE
PROGRAMMABLE
ALMOST EMPTY FLAG
(active LOW)
t_CHMFS t_CHMFH
t_CHMCLK
t_CHMSKEW3 t_CHMFO
PORT A CLOCK
READ ENABLE
Delta39K™ ISR™
CPLD Family
t_CHMFO
t_CHMFS
t_CHMFH
PORT B CLOCK
WRITE ENABLE
PROGRAMMABLE
ALMOST FULL FLAG
(Active LOW)
PORT A CLOCK
READ ENABLE
t_CHMFO
t_CHMCLK
t_CHMSKEW3
t_CHMFO
Document #: 38-03039 Rev. *H
Page 36 of 86