39K30 Datasheet, PDF (35/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Channel Memory Synchronous FIFO Full/Read Timing
PORT A CLOCK
READ ENABLE
REGISTERED
OUTPUT
t_CHMFS
t_CHMFH
t_CHMCLK
t_CHMFRDV
Delta39K™ ISR™
CPLD Family
FULL FLAG
(Active LOW)
PORT B CLOCK
t_CHMSKEW1 t_CHMFO
t_CHMFO
WRITE ENABLE
REGISTERED
INPUT
t_CHMS
t_CHMH
Document #: 38-03039 Rev. *H
Page 35 of 86