39K30 Datasheet, PDF (40/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Delta39K Part Numbers (Ordering Information) (continued)
Device
39K200
Speed
(MHz)
Ordering Code
181 CY39200V208-181NTC
CY39200V484-181BBC
CY39200V388-181MGC
CY39200V676-181MBC
125 CY39200V208-125NTC
CY39200V484-125BBC
CY39200V388-125MGC
CY39200V676-125MBC
CY39200V208-125NTI
CY39200V484-125BBI
83 CY39200V208-83NTC
CY39200V484-83BBC
CY39200V388-83MGC
CY39200V676-83MBC
CY39200V208-83NTI
CY39200V484-83BBI
Package
Name
Package Type
Self-Boot Operating
Solution Range
NT208 208-Lead Enhanced Quad Flat Pack
Commercial
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
÷
MB676 676-Lead Fine Pitch Ball Grid Array
÷
NT208 208-Lead Enhanced Quad Flat Pack
Commercial
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
÷
MB676 676-Lead Fine Pitch Ball Grid Array
÷
NT208 208-Lead Enhanced Quad Flat Pack
Industrial
BB484 484-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
Commercial
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
÷
MB676 676-Lead Fine Pitch Ball Grid Array
÷
NT208 208-Lead Enhanced Quad Flat Pack
Industrial
BB484 484-Lead Fine Pitch Ball Grid Array
CPLD Boot EEPROM^[17] Part Numbers (Ordering Information)
Device
2 Mbit
1 Mbit
512 Kbit
Speed
(MHz)
15
10
15
10
15
10
Ordering Code
AT17LV002-10JC
AT17LV002-10JC
AT17LV010-10JC
AT17LV010-10JI
AT17LV512-10JC
AT17LV512-10JI
Package
Name
Package Type
Operating
Range
20J 20-Lead Plastic Leaded Chip Carrier Commercial
20J 20-Lead Plastic Leaded Chip Carrier Industrial
20J 20-Lead Plastic Leaded Chip Carrier Commercial
20J 20-Lead Plastic Leaded Chip Carrier Industrial
20J 20-Lead Plastic Leaded Chip Carrier Commercial
20J 20-Lead Plastic Leaded Chip Carrier Industrial
Recommended ATMEL CPLD Boot EEPROM for corresponding Delta39K CPLDs
CPLD Device
39K30
39K50
39K100
39K165
39K200
Recommended boot EEPROM
AT17LV512
AT17LV512
AT17LV010
AT17LV002
AT17LV002
Note:
17. Refer to the data sheets at www.atmel.com for detailed architectural and timing information.
Document #: 38-03039 Rev. *H
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