39K30 Datasheet, PDF (43/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Package Diagrams (continued)
256-Ball FBGA (17 x 17 mm) BB256
TOP VIEW
PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
A1 _C
SEATING PLANE
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K)
Ø0.50±0.05(256X)-ALL OTHER DEVICES
PIN 1 CORNER
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
B
A
1.00
7.50
15.00
17.00±0.10
0.20(4X)
REFERENCE JEDEC MO-192
A1 0.36 0.56
A 1.40 MAX. 1.60 MAX.
51-85108-*D
Document #: 38-03039 Rev. *H
Page 43 of 86