39K30 Datasheet, PDF (21/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Channel Memory Timing Parameter Descriptions Over the Operating Range (continued)
Parameter
Description
Internal Parameters
t_CHMCHAA
Asynchronous channel memory access time from input of channel memory to output of channel memory
Switching Characteristics — Parameter Values Over the Operating Range
233
200
Parameter
Min. Max. Min. Max.
Combinatorial Mode Parameters
t_PD
7.2
7.5
t_EA
4.5
5.0
t_ER
4.5
5.0
t_PRR
6.0
6.0
t_PRO
9.5
10
t_PRW
3.3
3.6
Synchronous Clocking Parameters
t_MCS
2.7
3.0
t_MCH
0
0
t_MCCO
5.8
6.0
t_IOS
1.0
1.0
t_IOH
0.9
1.0
t_IOCO
3.8
4.0
t_SCS
3.4
3.5
t_SCS2
4.3
4.5
t_ICS
4.5
5.0
t_OCS
4.5
5.0
t_CHZ
3.5
3.5
t_CLZ
1.5
1.5
f_MAX
294
286
f_MAX2
233
222
Product Term Clocking Parameters
t_MCSPT
2.7
3.0
t_MCHPT
0.9
1.0
t_MCCOPT
7.5
8.0
t_SCS2PT
6.0
6.5
Channel Interconnect Parameters
t_CHSW
0.9
1.0
t_CL2CL
1.8
2.0
Miscellaneous Parameters
t_CPLD
t_MCCD
PLL Parameters
2.8
0.22
3.0
0.25
t_MCCJ
t_DWSA
t_DWOSA
t_LOCK
–150
–1.35
–150
150
–0.85
150
250
–150
–1.35
–150
150
–0.85
150
250
181
Min. Max.
8.5
5.6
5.3
6.0
10.5
4.0
3.5
0
7.0
1.2
1.2
4.5
3.6
5.5
5.5
5.5
3.8
1.5
278
181
3.3
1.4
8.8
7.2
1.2
2.3
3.3
0.28
–150
–1.35
–150
150
–0.85
150
250
125
Min. Max.
10
9.0
9.0
8.0
13
6.0
5.0
0
10
2.0
2.0
7.0
6.4
8.0
8.0
8.0
6.0
1.5
156
125
5.0
2.0
11.0
10.0
1.7
2.8
4.0
0.35
–180 180
–2.0 –1.5
–180 180
250
83
Min. Max.
15
10
10
10
15
7.0
6.7
0
12
2.5
2.5
8.0
9.6
12
12
12
7.0
1.5
104
83
6.0
2.5
15.0
15.0
2.0
3.0
5.0
0.38
–200 200
–2.9 –2.4
–200 200
250
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ps
ms
Document #: 38-03039 Rev. *H
Page 21 of 86