39K30 Datasheet, PDF (30/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Channel Memory DP Asynchronous Timing
Delta39K™ ISR™
CPLD Family
ADDRESS
WRITE
ENABLE
DATA
INPUT
OUTPUT
A_n-1
A_n
t_CHMSA
t_CHMPWE
t_CHMHA
A_n+1
D_n–1
t_CHMSD
D_n
t_CHMHD
t_CHMAA
D_n
D_n+1
A_n+2
t_CHMAA
Channel Memory Internal Clocking
MACROCELL INPUT
CLOCK
CHANNEL MEMORY
INPUT CLOCK
t_CHMMACS1
CHANNEL MEMORY
OUTPUT CLOCK
t_CHMMACS2
t_MACCHMS1
t_MACCHMS2
Document #: 38-03039 Rev. *H
Page 30 of 86