39K30 Datasheet, PDF (51/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Table 11. 208 EQFP/PQFP Pin Table (continued)
Pin
188^[19]
189^[19]
190^[19]
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
CY39030
IO7
IO7
IO/V_REF7
V_CCIO7
IO7
IO7
IO7
IO7
IO/V_REF7
IO7
IO7
V_CCIO7
IO7
IO/V_REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
CY39050
IO7
IO7
IO/V_REF7
V_CCIO7
IO7
IO7
IO7
IO7
IO/V_REF7
IO7
IO7
V_CCIO7
IO7
IO/V_REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
CY39100
IO7
IO7
IO/V_REF7
V_CCIO7
IO7
IO7
IO7
IO7
IO/V_REF7
IO7
IO7
V_CCIO7
IO7
IO/V_REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
CY39165
IO7
IO7
IO/V_REF7
V_CCIO7
IO7
IO7
IO7
IO7
IO/V_REF7
IO7
IO7
V_CCIO7
IO7
IO/V_REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
CY39200
IO7
IO7
IO/V_REF7
V_CCIO7
IO7
IO7
IO7
IO7
IO/V_REF7
IO7
IO7
V_CCIO7
IO7
IO/V_REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
Table 12. 388 BGA Pin Table
Pin
CY39050
CY39100
CY39165
CY39200
A1
GND
GND
GND
GND
A2
NC
IO7
IO7
IO7
A3
IO7
IO7
IO7
IO7
A4
IO7
IO7
IO7
IO7
A5
IO7
IO7
IO7
IO7
A6
IO7
IO7
IO7
IO7
A7
IO7
IO7
IO7
IO7
A8
NC
IO/VREF7
IO/VREF7
IO/VREF7
A9
IO7
IO7
IO7
IO7
A10
IO7
IO7
IO7
IO7
A11
A12
A13^[19]
A14^[19]
IO/V_REF7
IO7
IO7
IO6
IO/V_REF7
IO7
IO7
IO6
IO/V_REF7
IO7
IO7
IO6
IO/V_REF7
IO7
IO7
IO6
A15
IO6
IO6
IO6
IO6
A16
GND
GND
GND
GND
A17
IO6
IO6
IO6
IO6
A18
IO6
IO6
IO6
IO6
Note:
19. Capacitance on these I/O pins meets the PCI spec (rev. 2.2), which requires IDSEL pin in a PCI design to have capacitance less than or equal to 8 pf. In the
document titled “Delta39K CPLD Family data sheet”, this spec is defined as C_PCI. All other I/O pins have a capacitance less than or equal to 10 pf.
Document #: 38-03039 Rev. *H
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