39K30 Datasheet, PDF (4/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
figure the devices without having design changes cause
pinout or timing changes in most cases. The Cypress ISR
function is implemented through a JTAG-compliant serial
interface. Data is shifted in and out through the TDI and TDO
pins respectively. Superior routability, simple timing, and the
ISR allows users to change existing logic designs while simul-
taneously fixing pinout assignments and maintaining system
performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The Delta39K
family also features user programmable bus-hold and slew
rate control capabilities on each I/O pin.
AnyVolt Interface
All Delta39KV devices feature an on-chip regulator, which
accepts 3.3V or 2.5V on the V_CC supply pins and steps it down
to 1.8V internally, the voltage level at which the core operates.
With Delta39K’s AnyVolt technology, the I/O pins can be
connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devices
are 3.3V-tolerant regardless of V_CCIO or V_CC settings.
Table 1.
Device
V_CC
39KV 3.3V or 2.5V
V_CCIO
3.3V or 2.5V or 1.8V or 1.5V^[5]
Global Routing Description
The routing architecture of the Delta39K is made up of
horizontal and vertical (H and V) routing channels. These
routing channels allow signals from each of the Delta39K
architectural components to communicate with one another. In
addition to the horizontal and vertical routing channels that
interconnect the I/O banks, channel memory blocks, and logic
block clusters, each LBC contains a Programmable Inter-
connect Matrix (PIM™), which is used to route signals
among the logic blocks and the cluster memory blocks.
Figure 2 is a block diagram of the routing channels that
interface within the Delta39K architecture. The LBC is exactly
the same for every member of the Delta39K CPLD family.
Logic Block Cluster (LBC)
The Delta39K architecture consists of several logic block
clusters, each of which have eight Logic Blocks (LB) and two
cluster memory blocks connected via a Programmable Inter-
connect Matrix (PIM) as shown in Figure 3. Each cluster
memory block consists of 8-Kbit single-port RAM, which is
configurable as synchronous or asynchronous. The cluster
memory blocks can be cascaded with other cluster memory
blocks within the same LBC as well as other LBCs to
implement larger memory functions. If a cluster memory block
is not specifically utilized by the designer, Cypress’s Warp
software can automatically use it to implement large blocks of
logic.
All LBCs interface with each other via horizontal and vertical
routing channels.
I/O Block
Note:
5. For HSTL only.
LB
LB
72
LB
LB
64
Cluster
LB
PIM
LB
LB
Cluster
Memory
Block
LB
Cluster
Memory
Block
Channel
Memory
Block
72 64
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
V-to-H
PIM
H-to-V
PIM
Figure 2. Delta39K Routing Interface
Document #: 38-03039 Rev. *H
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