39K30 Datasheet, PDF (23/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
I/O Standard
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
Output Delay Adjustments
Fast Slew Rate
Slow Slew Rate
(additional delay to fast slew rate)
Input Delay Adjustments
t_IOD
t_EA
t_ER
–0.02 0.4
0
t_IODSLOW
2.0
t_EASLOW t_ERSLOW t_IOIN
2.0
2.0
0.9
t_CKIN
0.5
t_IOREGPIN
0.6
–0.22 0.2
0
2.0
2.0
2.0
0.9
0.5
0.6
0.94
0.9
0.5
2.0
2.0
2.0
0.5
0.5
0.3
0.79
0.8
0.5
2.0
2.0
2.0
0.5
0.5
0.3
0.77
0.5
0.1
2.0
2.0
2.0
0.5
0.5
0.3
0.44
0.6
0
2.0
2.0
2.0
0.5
0.5
0.3
Cluster Memory Timing Parameter Values Over the Operating Range
233
Parameter
Min. Max.
Asynchronous Mode Parameters
t_CLMAA
10.2
t_CLMPWE
5.5
t_CLMSA
1.8
t_CLMHA
0.9
t_CLMSD
5.5
t_CLMHD
0.4
Synchronous Mode Parameters
t_CLMCYC1
9.5
t_CLMCYC2
5.0
t_CLMS
2.8
t_CLMH
0
t_CLMDV1
10
t_CLMDV2
7.0
t_CLMMACS1
7.7
t_CLMMACS2
4.5
t_MACCLMS1
3.6
t_MACCLMS2
6.0
Internal Parameters
t_CLMCLAA
6
200
Min. Max.
11
6
2.0
1.0
6.0
0.5
10
5.0
3.0
0
11
7.5
8.0
5.0
4.0
6.5
6
181
Min. Max.
12
6.5
2.2
1.1
6.5
0.6
10.5
5.5
3.8
0
12
8.0
8.5
5.5
4.4
7.0
6.5
125
Min. Max.
17
10
3.2
1.8
10
0.9
15
8.0
4.0
0
17
10
12
8.0
6.6
10
10
Channel Memory Timing Parameter Values Over the Operating Range
233
200
Parameter
Min. Max. Min. Max.
Dual-Port Asynchronous Mode Parameters
t_CHMAA
t_CHMPWE
t_CHMSA
t_CHMHA
t_CHMSD
t_CHMHD
t_CHMBA
10
11
5.5
6.0
1.8
2.0
0.9
1.0
5.5
6.0
0.4
0.5
8.5
9.0
181
Min. Max.
12
6.5
2.2
1.1
6.5
0.6
10.0
125
Min. Max.
17
10
3.2
1.8
10
0.9
14.0
83
Min. Max.
20
12
4.0
2.0
12
1.0
20
10.0
5.0
0
20
15
15
10
8.0
12
12
83
Min. Max.
20
12
4.0
2.0
12
1.0
16.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
Document #: 38-03039 Rev. *H
Page 23 of 86