39K30 Datasheet, PDF (29/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Cluster Memory Output Register Timing (Asynchronous Inputs)
ADDRESS
WRITE
ENABLE
INPUT
t_CLMCYC2
GLOBAL CLOCK
(OUTPUT REGISTER)
t_CLMDV2
REGISTERED
OUTPUT
Cluster Memory Output Register Timing (Synchronous Inputs)
ADDRESS
WRITE
ENABLE
INPUT
GLOBAL CLOCK
(INPUT REGISTER)
GLOBAL CLOCK
(OUTPUT REGISTER)
REGISTERED
OUTPUT
t_CLMS
t_CLMCYC2
t_CLMH
t_CLMDV2
Delta39K™ ISR™
CPLD Family
Document #: 38-03039 Rev. *H
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