39K30 Datasheet, PDF (20/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Cluster Memory Timing Parameter Descriptions Over the Operating Range (continued)
Parameter
Description
t_MACCLMS2
Macrocell clock to cluster memory output clock in the same cluster
Internal Parameters
t_CLMCLAA
Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
Channel Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Dual Port Asynchronous Mode Parameters
t_CHMAA
Channel memory access time. Delay from address change to Read data out
t_CHMPWE
Write enable pulse width
t_CHMSA
Address set-up to the beginning of Write enable with both signals from the same I/O block
t_CHMHA
Address hold after the end of Write enable with both signals from the same I/O block
t_CHMSD
Data set-up to the end of Write enable
t_CHMHD
Data hold after the end of Write enable
t_CHMBA
Channel memory asynchronous dual port address match (busy access time)
Dual Port Synchronous Mode Parameters
t_CHMCYC1
Clock cycle time for flow through Read and Write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
t_CHMCYC2
Clock cycle time for pipelined Read and Write operations (from channel memory input register through the
memory to channel memory output register)
t_CHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
t_CHMH
Address, data, and WE hold time of pin inputs, relative to a global clock
t_CHMDV1
Global clock to data valid on output pins for flow through data
t_CHMDV2
Global clock to data valid on output pins for pipelined data.
t_CHMBDV
Channel memory synchronous dual-port address match (busy, clock to data valid)
t_CHMMACS1
Channel memory input clock to macrocell clock in the same cluster
t_CHMMACS2
Channel memory output clock to macrocell clock in the same cluster
t_MACCHMS1
Macrocell clock to channel memory input clock in the same cluster
t_MACCHMS2
Macrocell clock to channel memory output clock in the same cluster
Synchronous FIFO Data Parameters
t_CHMCLK
Read and Write minimum clock cycle time
t_CHMFS
Data, Read enable, and Write enable set-up time relative to pin inputs
t_CHMFH
Data, Read enable, and Write enable hold time relative to pin inputs
t_CHMFRDV
Data access time to output pins from rising edge of Read clock (Read clock to data valid)
t_CHMMACS
Channel memory FIFO Read clock to macrocell clock for Read data
t_MACCHMS
Macrocell clock to channel memory FIFO Write clock for Write data
Synchronous FIFO Flag Parameters
t_CHMFO
t_CHMMACF
t_CHMFRS
t_CHMFRSR
t_CHMFRSF
t_CHMSKEW1
t_CHMSKEW2
t_CHMSKEW3
Read or Write clock to respective flag output at output pins
Read or Write clock to macrocell clock with FIFO flag
Master Reset Pulse Width
Master Reset Recovery Time
Master Reset to Flag and Data Output Time
Read/Write Clock Skew Time for Full Flag
Read/Write Clock Skew Time for Empty Flag
Read/Write Clock Skew Time for Boundary Flags
Document #: 38-03039 Rev. *H
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