39K30 Datasheet, PDF (76/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
CY39050
CY39100
CY39165
CY39200
Y7
IO2
IO2
IO2
IO2
Y8
NC
IO2
IO2
IO2
Y9
NC
IO2
IO2
IO2
Y10
IO/V_REF2
Y11
IO2
IO/V_REF2
IO2
IO/V_REF2
IO2
IO/V_REF2
IO2
Y12
IO3
IO3
IO3
IO3
Y13
IO/V_REF3
Y14
IO3
IO/V_REF3
IO3
IO/V_REF3
IO3
IO/V_REF3
IO3
Y15
IO3
IO3
IO3
IO3
Y16
IO3
IO3
IO3
IO3
Y17
IO3
IO3
IO3
IO3
Y18
NC
IO3
IO3
IO3
Y19
NC
IO3
IO3
IO3
Y20
NC
NC
NC
IO3
Y21
NC
NC
NC
IO3
Y22
NC
NC
NC
IO3
AA1
GND
GND
GND
GND
AA2
GND
GND
GND
GND
AA3
NC
NC
IO2
IO2
AA4
AA5
AA6
V_CCIO2
IO/V_REF2
IO2
V_CCIO2
IO/V_REF2
IO2
V_CCIO2
IO/V_REF2
IO2
V_CCIO2
IO/V_REF2
IO2
AA7
NC
IO2
IO2
IO2
AA8
IO2
IO2
IO2
IO2
AA9
NC
AA10
NC
NC
V_CCIO2
V_CCIO2
IO2
IO2
IO2
AA11
IO2
IO2
IO2
IO2
AA12
IO3
IO3
IO3
IO3
AA13
IO3
IO3
IO3
IO3
AA14
NC
AA15
IO3
AA16
NC
AA17
NC
NC
V_CCIO3
V_CCIO3
IO3
IO3
IO3
IO3
IO3^[20]
IO3
IO3
IO3^[20]
IO3
AA18
AA19
AA20
IO/V_REF3
V_CCIO3
NC
IO/V_REF3
V_CCIO3
NC
IO/V_REF3
V_CCIO3
NC
IO/V_REF3
V_CCIO3
IO3
AA21
GND
GND
GND
GND
AA22
GND
GND
GND
GND
AB1
GND
GND
GND
GND
AB2
GND
GND
GND
GND
AB3
NC
NC
IO/V_REF2
IO/V_REF2
AB4
NC
NC
IO/V_REF2
IO/V_REF2
Note:
20. These I/Os have a slightly higher t_PD (propagation delay) than the rest of the pins. The use of these pins on the same packages of different densities or the
pins in the same relative position in smaller or larger FBGAs for signals with critical timing should be avoided. When first implementing a design in these
packages, the timing-driven routing of Warp 6.2 and later versions will ensure these pins are avoided when routing critical signal.
Document #: 38-03039 Rev. *H
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