39K30 Datasheet, PDF (45/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Package Diagrams (continued)
676-Ball FBGA (27 x 27 x 1.6 mm) BB676/MB676
51-85125-*B
Pin Tables
Table 8. Pin Definition Table
Pin Name
GCLK0-3
GCTL0-3
GND
IO/V_REF0
IO/V_REF1
IO/V_REF2
IO/V_REF3
IO/V_REF4
IO/V_REF5
IO/V_REF6
IO/V_REF7
IO
IO6/Lock
MSEL
Function
Input
Input
Ground
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Description
Global Clock signals 0 through 3
Global Control signals 0 through 3
Ground
Dual function pin: IO or Reference Voltage for Bank 0
Dual function pin: IO or Reference Voltage for Bank 1
Dual function pin: IO or Reference Voltage for Bank 2
Dual function pin: IO or Reference Voltage for Bank 3
Dual function pin: IO or Reference Voltage for Bank 4
Dual function pin: IO or Reference Voltage for Bank 5
Dual function pin: IO or Reference Voltage for Bank 6
Dual function pin: IO or Reference Voltage for Bank 7
Input or Output pin
Dual function pin: IO in Bank 6 or PLL lock output signal
Mode Select Pin (see Table 9)
Document #: 38-03039 Rev. *H
Page 45 of 86