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39K30 Datasheet, PDF (1/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM | |||
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Delta39K⢠ISRâ¢
CPLD Family
Features
⢠High density
â 30K to 200K usable gates
â 512 to 3072 macrocells
â 136 to 428 maximum I/O pins
â Twelve dedicated inputs including four clock pins,
four global I/O control signal pins and four JTAG
interface pins for boundary scan and reconfig-
urability
⢠Embedded memory
â 80K to 480K bits embedded SRAM
⢠16K to 96K bits of (dual-port) channel memory
⢠High speed â 233-MHz in-system operation
⢠AnyVolt⢠interface
â 3.3V, 2.5V,1.8V, and 1.5V I/O capability
⢠Low-power operation
â 0.18-mm six-layer metal SRAM-based logic process
â Full-CMOS implementation of product term array
â Standby current as low as 5mA
⢠Simple timing model
â No penalty for using full 16 product terms/macrocell
â No delay for single product term steering or sharing
⢠Flexible clocking
â Spread Aware⢠PLL drives all four clock networks
⢠Allows 0.6% spread spectrum input clocks
⢠Several multiply, divide and phase shift options
â Four synchronous clock networks per device
â Locally generated product term clock
â Clock polarity control at each register
CPLDs at FPGA Densitiesâ¢
⢠Carry-chain logic for fast and efficient arithmetic opera-
tions
⢠Multiple I/O standards supported
â LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
⢠Compatible with NOBLâ¢, ZBTâ¢, and QDR⢠SRAMs
⢠Programmable slew rate control on each I/O pin
⢠User-programmable Bus Hold capability on each I/O pin
⢠Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,
rev. 2.2)
⢠CompactPCI hot swap ready
⢠Multiple package/pinout offering across all densities
â 208 to 676 pins in PQFP, BGA, and FBGA packages
â Simplifies design migration across density
â Self-Boot⢠solution in BGA and FBGA packages
⢠In-System Reprogrammable⢠(ISRâ¢)
â JTAG-compliant on-board programming
â Design changes do not cause pinout changes
⢠IEEE1149.1 JTAG boundary scan
Development Software
⢠Warp®
â IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
â Active-HDL FSM graphical finite state machine editor
â Active-HDL SIM post-synthesis timing simulator
â Architecture Explorer for detailed design analysis
â Static Timing Analyzer for critical path analysis
â Available on Windows 95/98/2000/XP⢠and
Windows NT⢠for $99
â Supports all Cypress programmable logic products
Delta39K⢠ISR CPLD Family Members
Device
Typical
Gates[1]
Cluster Channel
memory memory Maximum
Macrocells (Kbits) (Kbits) I/O Pins
39K30
16K â 48K
512
64
16
174
39K50
23K â 72K
768
96
24
218
39K100 46K â 144K
1536
192
48
302
39K165 77K â 241K
2560
320
80
386
39K200 92K â 288K
3072
384
96
428
Notes:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby ICC values are with PLL not utilized, no output load and stable inputs.
fMAX2
(MHz)
233
233
222
181
181
Speed-tPD
Pin-to-Pin
(ns)
7.2
7.2
7.5
8.5
8.5
Standby ICC[2]
TA = 25°C
3.3/2.5V
5 mA
5 mA
10 mA
20 mA
20 mA
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose ⢠CA 95134 ⢠408-943-2600
Document #: 38-03039 Rev. *H
Revised August 1, 2003
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