39K30 Datasheet, PDF (31/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Channel Memory Internal Clocking 2
MACROCELL INPUT
CLOCK
FIFO READ
CLOCK
t_CHMMACS
FIFO WRITE
CLOCK
FIFO READ OR
WRITE CLOCK
Channel Memory DP SRAM Flow-Through R/W Timing
CLOCK
ADDRESS
A_n–1
t_CHMS
t_CHMCYC1
t_CHMH
A_n
A_n+1
Delta39K™ ISR™
CPLD Family
t_MACCHMS
t_CHMMACF
A_n+2
A_n+3
WRITE
ENABLE
DATA
INPUT
D_n–1
OUTPUT
D_n–1
t_{CHMS tCHMH}
t_CHMDV1
D_n+1
t_CHMDV1
t_CHMDV1
D_n+3
t_CHMDV1
D_n
D_n+1
D_n+2
D_n+3
Document #: 38-03039 Rev. *H
Page 31 of 86