39K30 Datasheet, PDF (28/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Cluster Memory Synchronous Flow-Through Timing
READ
GLOBAL
CLOCK
t_CLMS
t_CLMH
ADDRESS
t_CLMS
t_CLMH
Delta39K™ ISR™
CPLD Family
WRITE
t_CLMCYC1
READ
t_CLMS
t_CLMH
WRITE
ENABLE
REGISTERED
INPUT
REGISTERED
OUTPUT
t_CLMDV1
t_CLMDV1
t_CLMDV1
Cluster Memory Internal Clocking
MACROCELL
INPUT CLOCK
CLUSTER MEMORY
INPUT CLOCK
t_CLMMACS1
t_CLMMACS2
CLUSTER MEMORY
OUTPUT CLOCK
t_MACCLMS1
t_MACCLMS2
Document #: 38-03039 Rev. *H
Page 28 of 86