39K30 Datasheet, PDF (32/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Channel Memory DP SRAM Pipeline R/W Timing
Delta39K™ ISR™
CPLD Family
CLOCK
ADDRESS
A_n–1
WRITE
ENABLE
t_CHMS
t_CHMCYC2
t_CHMH
A_n
t_CHMS ^tCHMH
A_n+1
A_n+2
A_n+3
DATA
INPUT
D_n–1
OUTPUT
D_n–1
t_CHMS ^tCHMH
D_n+1
t_CHMDV2
t_CHMDV2
D_n+3
t_CHMDV2
D_n
D_n+1
D_n+2
Dual-Port Asynchronous Address Match Busy Signal
ADDRESS A
B_n
A_n
ADDRESS B
A_n–1
A_n
t_CHMBA
ADDRESS
MATCH
A_n+1
t_CHMBA
Document #: 38-03039 Rev. *H
Page 32 of 86