39K30 Datasheet, PDF (85/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Pin
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
CY39100
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
CY39165
GND
GND
NC
V_CCIO3
NC
NC
NC
NC
V_CCIO3
NC
NC
NC
NC
GND
CY39200
GND
GND
NC
V_CCIO3
NC
IO3
IO3
IO3
V_CCIO3
IO3
IO3
IO3
NC
GND
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trademark of IDT. QDR is a trademark of Micron, IDT, and Cypress Semiconductor. Warp is a registered trademark, and NoBL,
Programmable Interconnect Matrix, PIM, Spread Aware, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, “CPLDs at FPGA
Densities,” True Vertical Migration, and Delta39K are trademarks, of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-03039 Rev. *H
Page 85 of 86
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
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