W641GG2JB Datasheet, PDF (94/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
7.3 DC & AC Logic Input Levels
7.3.1 DC & AC Logic Input Levels (0 °C ≤ T_c ≤ 105 °C)
Parameter
Symbol
Limit Values
Min.
Max.
Unit Note
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logic low, DC, RESET pin
Input Logic High, DC, MF pin
Input Logic Low,DC, MF pin
V_IH(DC)
V_IL(DC)
V_IH(AC)
V_IL(AC)
V_IHR(DC)
V_ILR(DC)
V_IHMF(DC)
V_ILMF(DC)
V_REF + 0.15
—
V_REF + 0.25
—
0.65 × V_DDQ
-0.3
V_DD
–0.3
—
V_REF -0.15
—
V_REF - 0.25
V_DDQ + 0.3
0.35 × V_DDQ
V_DD + 0.3
0
V
1,2
V
1,2
V
1,3,4
V
1,3,4
V
V
V
5
V
Notes :
1. for 1.8 V V_DD/V_DDQ power supply.
2. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a
valid level.
3. Input slew rate = 3 V/ns. If the input slew rate is less than 3 V/ns, input timing may be compromised. All slew rates are measured between VIL(AC)
and V_IH(AC).
4. V_IH overshoot: V_IH(max) = V_DDQ+0.5V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. V_IL undershoot:
V_IL(min) = 0 V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
5. The MF pin must be hard-wired on board to either V_DD or V_SS.
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Publication Release Date: Apr, 22, 2011
Revision A01-002