W641GG2JB Datasheet, PDF (60/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.14 Write - Basic Sequence
0
CLK#
CLK
Com. WR
Addr. B/C
WDQS
DQ
WDQS
DQ
1
2
3
4
5
6
7
8
N/D
DES
DES
DES
DES
DES
DES
DES
WL = 3
WL = 4
D0 D1 D2 D3
D0 D1 D2 D3
Com. WR
Addr. B/C
N/D
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WDQS
DQ
WL = 3
D0 D1 D2 D3
WDQS
DQ
WL = 4
B / C: Bank / Column address
WR : WRITE
NOP : No Operation
D0 D1 D2 D3
DES : Deselect
N/D : NOP or DES
Com. : Command
Addr. : Address B / C
D# : Data to B / C
WL : Write Latency
Don’t care
Notes :
1. Shown with nominal value of t_DQSS.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
3. When NOPs are applied on the command bus, the WDQS and the DQ busses remain stable High.
4. When DESs are applied on the command bus, the status of the WDQS and DQ busses is unknown.
- 60 -
Publication Release Date: Apr, 22, 2011
Revision A01-002