W641GG2JB Datasheet, PDF (39/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.5.2.2 Number of Legs used for Terminator and Driver Self Calibration
ADD / CMD
CKE (at RES)
0
1
Terminator
00
DQ
10
11
Termination
Number of Legs
ZQ/2
2
ZQ
1
EMRS[3:2]
Disabled
0
ZQ/4
4
ZQ/2
2
Driver
PMOS
NMOS
Note :
1. EMRS[3:2] = 00 disables the ADD and CMD terminations as well.
ZQ/6
6
ZQ/6
6
Note
1
Figure represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted in such a way that the
VDDQ voltage is divided equally between the PMOS device and the ZQ resistor. The best bit pattern will cause the comparator to
switch the PMOS Match signal output value. In a second step, the NFET is calibrated against the already calibrated PFET. In the
same manner, the best control bit combination will cause the comparator to switch the NMOS Match signal output value.
6.5.2.3 Self Calibration of PMOS and NMOS Legs
VDDQ
Strength Control
[2:0]
PMOS
Calibration
VSSQ
VDDQ
NMOS
Calibration
ZQ
VSSQ
VDDQ / 2
Strength Control
Match
[2:0]
VDDQ / 2
VSSQ
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Publication Release Date: Apr, 22, 2011
Revision A01-002