W641GG2JB Datasheet, PDF (57/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.13 Writes (WR)
6.13.1 Write - Basic Information
Write bursts are initiated with a WR command, as shown in Figure. The column and bank addresses are provided with the WR
command, and Auto Precharge is either enabled or disabled for that access. The length of the burst initiated with a WR command is
four or eight depending on the mode register setting. There is no interruption of WR bursts. The two least significant address bits A0
and A1 are ―Don‘t Care‖.
For WR commands with Autoprecharge the row being accessed is precharged t_WR/A after the completion of the burst. If
t_RAS(min) is violated the begin of the internal Autoprecharge will be performed one cycle after t_RAS(min) is met. WR, the write
recovery time for write with Autoprecharge can be programmed in the Mode Register. Choosing high values for WR will prevent the
chip to delay the internal Autoprecharge in order to meet t_RAS(min).
During WR bursts data will be registered with the edges of WDQS. The write latency can be programmed during Extended Mode
Register Set. The first valid data is registered with the first valid rising edge of WDQS following the WR command. The externally
provided WDQS must switch from HIGH to LOW at the beginning of the preamble. There is also a postamble requirement before the
WDQS returns to HIGH. The WDQS signal can only transition when data is applied at the chip input and during pre- and
postambles. t_DQSS is the time between WR command and first valid rising edge of WDQS. Nominal case is when WDQS edges are
aligned with edges of external CLK. Minimum and maximum values of t_DQSS define early and late WDQS operation. Any input data
will be ignored before the first valid rising WDQS transition.
t_DQSL and t_DQSH define the width of low and high phase of WDQS. The sum of t_DQSL and t_DQSH has to be t_CK. Back to back WR
commands are possible and produce a continuous flow of input data.
For back to back WR, t_CCD has to be met. Any WR burst may be followed by a subsequent RD command. Figure (Write followed by
Read) shows the timing requirements for a WR followed by a RD. In this case the delay between the WR command and the
following RD may be zero for access across the two 8 bank segments (t_{WTR_RR} = 1 t_CK) as shown in Figure (Write followed by
Read on different ranks in 2-CS mode).
A WR may also be followed by a PRE command to the same bank. t_WR has to be met as shown in Figure (Write followed by
Precharge on same bank).
Setup and hold time for incoming DQs and DMs relative to the WDQS edges are specified as t_DS and t_DH. DQ and DM input pulse
width for each input is defined as t_DIPW. The input data is masked if the corresponding DM signal is high.
All iming parameters are defined with graphics DRAM terminations on.
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Publication Release Date: Apr, 22, 2011
Revision A01-002