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W641GG2JB Datasheet, PDF (104/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM
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W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
Limit Values
Parameter
CAS latency Symbol
650
700
min max min max
Data-in and Data Mask to WDQS Setup Time
tDS
0.18
— 0.18
—
Data-in and Data Mask to WDQS Hold Time
tDH
0.18
— 0.18
—
Data-in and DM input pulse width (each input)
tDIPW
0.40
— 0.40
—
DQS input low pulse width
tDQSL
0.40
— 0.40
—
DQS input high pulse width
tDQSH
0.40
— 0.40
—
DQS Write Preamble Time
tWPRE
0.75 1.25 0.75 1.25
DQS Write Postamble Time
tWPST
0.75 1.25 0.75 1.25
Write Recovery Time
tWR
10
—
10
—
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
Read Preamble
Read Postamble
Data-out high impedance time from CLK
Data-out low impedance time from CLK
DQS edge to Clock edge skew
DQS edge to output data edge skew
Data hold skew factor
Data output hold time from DQS
tAC
–0.25 0.25 –0.25 0.25
tRPRE
0.75 1.25 0.75 1.25
tRPST
0.75 1.25 0.75 1.25
tHZ
tACmin
tACmax tACmin
tACmax
tLZ
tACmin
tACmax tACmin
tACmax
tDQSCK –0.25 0.25 –0.25 0.25
tDQSQ
—
0.16 —
0.16
tQHS
—
0.16 —
0.16
tQH
tHP–tQHS
Refresh/Power Down Timing
Refresh Period (8192 cycles)
Average periodic Auto Refresh interval
Delay from AREF to next ACT/ AREF
Self Refresh Exit time
Power Down Exit time
tREF
—
32
—
32
tREFI
3.9
3.9
tRFC
59
—
59
—
tXSC
1000
— 1000
—
tXPN
6
—
6
—
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
Termination update Keep Out timing
Rev. ID EMRS to DQ on timing
REV. ID EMRS to DQ off timing
tATS
10
—
10
—
tATH
10
—
10
—
tKO
10
—
10
—
tRIDon
—
20
—
20
tRIDoff
—
20
—
20
800
min max
0.18 —
0.18 —
0.40 —
0.40 —
0.40 —
0.75 1.25
0.75 1.25
10
—
–0.25
0.75
0.75
tACmin
tACmin
–0.25
—
—
0.25
1.25
1.25
tACmax
tACmax
0.25
0.16
0.16
—
32
3.9
59
—
1000 —
6
—
10
—
10
—
10
—
—
20
—
20
Unit
MHz
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ms
µs
ns
tCK
tCK
ns
ns
ns
ns
ns
Note
5,13
5,13
11
4
15
- 104 -
Publication Release Date: Apr, 22, 2011
Revision A01-002
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