W641GG2JB Datasheet, PDF (14/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
5.1.2 Function Truth Table for more than one Activated Bank
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the chip‘s
multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions are illegal.
Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the assumption that
there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank t_RRD, t_RTW and t_WTR have to
be taken always into account.
5.1.2.1 Function Truth Table
Current State
Ongoing action on bank n
Possible action in parallel on bank m
ACTIVE
ACTIVATE¹
WRITE³
WRITE/A
READ⁷⁾
READ/A⁹⁾
PRECHARGE¹⁰
PRECHARGE ALL ¹⁰
POWER DOWN ENTRY¹²
ACT, PRE, WRITE, WRITE/A, READ, READ/A²
ACT, PRE, WRITE, WRITE/A, READ, READ/A⁴
ACT, PRE, WRITE, WRITE/A, READ⁶
ACT, PRE, WRITE, WRITE/A, READ, READ/A⁸
ACT, PRE, WRITE, WRITE/A, READ, READ/A ⁸
ACT, PRE, WRITE, WRITE/A, READ, READ/A¹¹
-
-
ACTIVATE 1)
ACT
POWER DOWN ENTRY ¹²
-
AUTO REFRESH¹³
-
IDLE
SELF REFRESH ENTRY ¹²
-
MODE REGISTER SET (MRS)¹⁴
-
EXTENDED MRS ¹⁴
-
EXTENDED MRS 2¹⁴
-
POWER DOWN
POWER DOWN EXIT¹⁵
-
SELF REFRESH
SELF REFRESH EXIT¹⁶
-
Notes :
1. Action ACTIVATE starts with issuing the command and ends after t_RCD.
2. During action ACTIVATE an ACT command on another bank is allowed considering t_RRD or t_{RRD_RR}, a PRE command on another bank is allowed
any time. WR, WR/A, RD and RD/A are always allowed.
3. Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge.
4. During action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank must be
separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before t_WTR or t_{WTR_RR} is met.
5. Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge.
6. During action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank has to be
separated by at least one NOP from the ongoing command. RD is not allowed before or t_WTR or t_{WTR_RR} is met. RD/A is not allowed during an
ongoing WRITE/A action.
7. Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
8. During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on another bank
has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to meet t_RTW.
9. Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
10. Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after t_RP.
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Publication Release Date: Apr, 22, 2011
Revision A01-002