W641GG2JB Datasheet, PDF(103/109 Page) Winbond

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W641GG2JB Datasheet, PDF (103/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

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W641GG2JB

1-Gbit GDDR3 Graphics SDRAM

7.10 AC Timings

Limit Values

Parameter

CAS latency Symbol

650

700

800

min max min max min max

Clock and Clock Enable

System frequency

Clock cycle to cycle period jitter

Clock high level width

Clock low level width

Minimum clock half period

CL =11

fCK11

450 700

CL =10

fCK10

450 700

CL = 9

fCK9

450 650

tJIT(cc)

0.06

tCH

0.45

tCL

0.45

tHP

0.45

Command and Address Setup and Hold Timing

450

800

0.06

0.45

Address/Command input setup time

Address/Command input hold time

Address/Command input pulse width

tIS

0.35

tIH

0.35

tIPW

0.7

Mode Register Set Timing

Mode Register Set cycle time

Mode Register Set to READ timing

tMRD

tMRDR

Row Timing

Row Cycle Time

tRC

Row Active Time

tRAS

ACT(a) to ACT(b) Command period

tRRD

ACT(a) to ACT(b) Command period (different rank) tRRD_RR

Row Precharge Time

tRP

Row to Column Delay Time for Reads

tRCDRD

Row to Column Delay Time for Writes

tRCDWR

Four Active Windows within Rank

tFAW

Column Timing

CAS(a) to CAS(b) Command period

tCCD

BL/2

Internal write to Read Command Delay

tWTR

Write to Read Command Delay (different rank)

tWTR_RR

Write to Write Command Delay (different rank)

tWTW_RR

Read to Write command delay

tRTW

tRTW(min) = CL + BL/2+ 2 - WL

Read to Read Command Delay (different rank)

tRTR_RR

Write Cycle Timing Parameters for Data and Data Strobe

Write command to first WDQS latching transition

tDQSS WLâ0.25 WL+0.25 WLâ0.25 WL+0.25 WLâ0.25 WL+0.25

Unit

MHz

tCK

Note

2,3

2,3,4

5,6

7,8

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Publication Release Date: Apr, 22, 2011

Revision A01-002

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