W641GG2JB Datasheet, PDF (44/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.6.3 Burst Length and Burst Type
6.6.3.1 Burst Length
Read and write accesses to the GDDR3 GRAPHICS SDRAM are burst-oriented, with a burst length of 4 or 8 as programmed inbits
A0-A2.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundaryis reached. The
block is uniquely selected by address bits A2-A7,A9.
The access order within a burst is fixed, and address bits A0 and A1 are ignored as shown in Table.
The only supported burst type is sequential.
6.6.3.2 Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3). This
device does not support the burst interleave mode.
6.6.3.2.1 Burst Definition
Burst Length
4
8
Column Address
A2
A1
A0
—
X
X
0
X
X
1
X
X
Order of Accesses within a Burst
0-1-2-3
0-1-2-3-4-5-6-7
4-5-6-7-0-1-2-3
The value applied at the balls A0 and A1 for the column address is ―Don‘t care‖.
6.6.4 CAS Latency
The READ latency, or CAS latency, is the delay between the registration of a READ command and the availability of the first piece
of output data. The latency is set using bits A4-A6.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with
clock edge n + m.
The high-speed option for CAS latencies of 13 to 20 shall be deleted or deactivated.
6.6.5 Write Latency
The WRITE latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first
bit of input data. The latency is set using bits A9-A11.
If a WRITE command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with
clock edge n + m.
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Publication Release Date: Apr, 22, 2011
Revision A01-002