W641GG2JB Datasheet, PDF (27/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
SREFEN
The Self Refresh function can be used to retain data in the GDDR3 Graphics RAM even if the rest of the system
is powered down. When entering the Self Refresh mode by issuing the SREFEN command, the GDDR3
Graphics RAM retains data without external clocking. The SREFEN command is initiated like an AREF
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering Self Refresh mode
and automatically enabled and reset upon exiting Self Refresh. (1000 cycles must then occur before a RD or
DTERDIS command can be issued) The active terminations remain enabled during Self Refresh. Input signals
except CKE are ―Don‘t Care‖. If two GDDR3 Graphics RAMs share the same Command and Address bus, Self
Refresh may be entered only for the two devices at the same time. In 2-CS mode, both memories may only
enter Self-Refresh, in parallel.
SREFEX
The SREFEX command is used to exit the Self Refresh mode. The DLL is automatically enabled and reset
upon exiting. The procedure for exiting Self Refresh requires a sequence of commands. First CLK and CLK#
must be stable prior to CKE going from LOW to HIGH. Once CKE is HIGH, the GDDR3 Graphics RAM must
receive only NOP/DESEL commands until t_XSC is satisfied. This time is required for the completion of any
internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and output
calibration is to apply NOPs for 1000 cycles before applying any other command to allow the DLL to lock and
the output drivers to recalibrate.
PWDNEN
The PWDNEN command enables the power down mode. It is entered when CKE is set low together with a
NOP/DESEL. The CKE signal is sampled at the rising edge of the clock. Once the power down mode is
initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power consumption. The DLL
remains active (unless disabled before with EMRS). All banks can be set to idle state or stay active. During
Power Down Mode, refresh operations cannot be performed; therefore the refresh conditions of the chip have
to be considered and if necessary Power Down state has to be left to perform an Auto Refresh cycle. If two
GDDR3 Graphics RAMs share the same Command and Address bus, Power down may be entered only for the
two devices at the same time.
A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode. Once CKE
PWDNEX is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until t_XPN is satisfied. After t_XPN
any command can be issued, but it has to comply with the state in which the power down mode was entered.
DTERDIS
Data Termination Disable (Bus snooping for RD commands): The Data Termination Disable Command is
detected by the device by snooping the bus for RD commands excluding CS. The GDDR3 Graphics RAM will
disable its Data terminators when a RD command is detected. The terminators are disabled starting at CL - 1
clocks after the RD command is detected and the duration is 4 clocks. In a 2CS system, both DRAM devices
will snoop the bus for RD commands to either device and both will disable their terminators if a RD command
is detected. The command and address terminators are always enabled. See Figure (ODT Disable Timing
during a READ command) for an example of when the data terminators are disabled during a RD command.
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Publication Release Date: Apr, 22, 2011
Revision A01-002