W641GG2JB Datasheet, PDF (66/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
6.15.6 Write followed by DTERDIS
1-Gbit GDDR3 Graphics SDRAM
0
CLK#
CLK
Com.
WR
Addr.
B/C
WDQS
DQ
Com.
WR
Addr.
B/C
WDQS
DQ
1
2
DTD
DES
WL = 3
N/D
DTD
WL = 4
3
4
5
6
7
8
9
10
DES
DES
DES
DES
DES
DES
DES
DES
CL = 7
D0 D1 D2 D3
DES
DES
DES
DES
DES
DES
DES
DES
CL = 7
D0 D1 D2 D3
B / C: Bank / Column address
WR : WRITE
DTD : DTERDIS
D# : Data to B / C
Com. : Command
Addr. : Address B / C
WL : Write Latency
CL : CAS Latency
DES : Deselect
N/D : NOP or Deselect
Don‘t care
Data Termination off
Notes :
1. Shown with nominal value of t_DQSS.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
3. A margin of one clock has been introduced in order to make sure that the data termination are still on when the last Write data
reaches the memory.
4. The minimum distance between Write and DTERDIS is one clock.
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Publication Release Date: Apr, 22, 2011
Revision A01-002