W641GG2JB Datasheet, PDF (15/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
11. During Action ACTIVE an ACT command on another banks is allowed considering t_RRD or t_{RRD_RR}. A PRE command on another bank is allowed
any time. WR, WR/A, RD and RD/A are always allowed.
12. During POWER DOWN and SELF REFRESH only the EXIT commands are allowed.
13. AUTO REFRESH starts with issuing the command and ends after t_RFC.
14. Actions MODE REGISTER SET, EXTENDED MODE REGISTER SET and EXTENDED MODE REGISTER 2 SET start with issuing the
command and ends after t_MRD.
15. Action POWER DOWN EXIT starts with issuing the command and ends after t_XPN.
16. Action SELF REFRESH EXIT starts with issuing the command and ends after t_XSC.
5.1.3 Function Truth Table for CKE
CKE
N-1
CKE
n
CURRENT STATE
COMMAND
ACTION
Power Down
X
L
L
Self Refresh
X
Stay in Power Down
Stay in Self Refresh
L
H
Power Down
Self Refresh
DESEL or NOP
DESEL or NOP
Exit Power Down
Exit Self Refresh ⁵
All Banks Idle
DESEL or NOP
Entry Precharge Power Down
H
L
Bank(s) Active
DESEL or NOP
Entry Active Power Down
Note
All Banks Idle
Auto Refresh
Entry Self Refresh
s:
1. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the GDDR3 Graphics RAM immediately prior to clock edge n.
3. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND.
4. All states and sequences not shown are illegal or reserved.
5. DESEL or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 1000 clock cycles is required
before applying any other valid command.
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Publication Release Date: Apr, 22, 2011
Revision A01-002