W641GG2JB Datasheet, PDF (68/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
6.15.8 Write followed by Precharge on same bank
1-Gbit GDDR3 Graphics SDRAM
0
CLK#
CLK
Com.
WR
Addr.
B/C
WDQS
1
2
3
4
5
6
7
8
9
10
N/D
DES
WL = 3
DES
DES
DES
DES
DES
DES
tWTR
PRE
DES
B
tRP
DQ
Com.
WR
Addr.
B/C
WDQS
DQ
D0 D1 D2 D3
N/D
DES
DES
DES
DES
DES
DES
DES
DES
PRE
WL = 4
tWTR
B
tRP
D0 D1 D2 D3
N/D : NOP or Deselect
DES : Deselect
Com. : Command
Addr. : Address B / C
WL : Write Latency
Don‘t care
B / C: Bank / Column address
WR : WRITE
PRE : PRECHARGE
Dx# : Data to B / Cx
Dy# : Data to B / Cy
Notes :
1. Shown with nominal value of t_DQSS.
2. WR and PRE commands are to same bank.
3. t_RAS requirement must also be met before issuing PRE command.
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
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Publication Release Date: Apr, 22, 2011
Revision A01-002