W641GG2JB Datasheet, PDF (38/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.5.2 Self Calibration for Driver and Termination
The output impedance is updated during all AREF commands. These updates are used to compensate for variations in supply
voltage and temperature. Impedance updates do not affect device operation. No activity on the Address, command and data bus is
allowed during a minimum Keep Out time t_KO after the Autorefresh command has been issued.
6.5.2.1 Termination update Keep Out time after Autorefresh command
CLK#
CLK
Com.
ARF
NOP
Add.
DQ
tKO
ARF : Autorefresh
Don’t care
Keep Out time
To guarantee optimum driver impedance after power-up, the GDDR3 GRAPHICS SDRAM needs 700 cycles after the clock is
applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 700 cycles, but
optimal output impedance will not be guaranteed.
The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration:
The PMOS device is calibrated against the external ZQ resistor value. First one PMOS leg is calibrated against ZQ. The number of
legs used for the terminators (DQ and ADD/CMD) and the PMOS driver is represented in Table . Next, one NMOS leg is calibrated
against the already calibrated PMOS leg. The NMOS driver uses 6 NMOS legs.
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Publication Release Date: Apr, 22, 2011
Revision A01-002