W641GG2JB Datasheet, PDF (48/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

6.7.2.2 Extended Mode Register Set Timing
CLK#
CLK
Command
PA
NOP
tRP
W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
EMRS
NOP
NOP
A.C.
tMRD
EMRS : Extended MRS command
PA : PREALL command
A.C. : Any command
Don't Care
6.7.3 Chip Select Mode
Mode
1-CS Mode, non-merged
2-CS Mode
1-CS Mode, merged
EMRS1[BA2]
0
0
1
1
EMRS2[A5]
0
1
0
1
Pin for CS1#
NA
J-3
NA
Pin for A12
J-2
NA
J-3
6.7.4 DLL
The DLL is enabled by default. If DLL-off operation is desired, the DLL must be disabled by setting bit A6 to '1'. Once enabled, the
DLL requires 1000 cycles to lock.
6.7.5 Write Recovery
The programmed WR value is used for the auto precharge feature along with tRP to determine tDAL. WR must be programmed
with a value greater than or equal to [RU{tWR/tCK}], where RU stands for round up, tWR is the analog value and tCK is the
operating clock cycle time.
The high-speed option for Write Recovery values of 11 to 20 shall be deleted or deactivated.
6.7.6 Termination Rtt
The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports ZQ / 4 and ZQ /
2 termination values. The termination may also be disabled for testing and other purposes. Data -, address - and command
- termination are disabled in parallel. The Termination Rtt are controlled independently from the Output Driver Impedance
values.
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Publication Release Date: Apr, 22, 2011
Revision A01-002