W641GG2JB Datasheet, PDF (105/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
1. f_CK(min), f_CK(max) for DLL on mode.
2. CLK and CLK# input slew rate must be greater than 3 V/ns.
3. t_HP is the lesser of t_CL minimum and t_CH minimum actually applied to the device CLK,CLK# inputs.
4. Timing is calculated for a clock frequecy of 700 MHz.
5. The input reference level for signals other than CLK and CLK# is V_REF.
6. Command/Address input slew rate = 3 V/ns. If the slew rate is less than 3 V/ns, timing is no longer referenced to the midpoint but to the Vil(AC)
maximum and V_iH(AC) minimum points .
7. This value of t_MRD applies only to the case where the "DLL reset"‘ bit is not activated.
8. tMRD is defined from MRS to any other command then READ.
9. t_RAS,max is 8*t_REFi.
10. t_CCD is either for gapless consecutive reads or gapless consecutive writes.
11. WTR and t_WR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
12. This parameter is defined for commands issued to rank m following rank n where m ≠ n. For all other type of access, standard
timing parameters do apply.
13. DQ and DM input slew rates must not deviate from WDQS by more than 10 percent. If the DQ/DM/WDQS slew rate is less than 3
V/ns, timing is no longer referenced to the midpoint but to the V_il(AC) maximum and V_iH(AC) minimum points.
14. Please round up t_RTW to the next integer of t_CK.
15. This parameter is defined per byte.
16. tAC +/-290ps when VDDmax.
17. Input slew rate = 2.2V/ns. If tIS/tIH higher than 550ps.
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Publication Release Date: Apr, 22, 2011
Revision A01-002