W641GG2JB Datasheet, PDF (102/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
7.9 Operating Current Ratings
SYM.
PARAMETER/CONDITION
TYP.
UNIT NOTES
650 700 800
IDD0
One Bank Activate Precharge Current: tCK = tCK(min); tRC =
tRC(min); CKE = HIGH; data bus inputs are
SWITCHING; address and command inputs are SWITCHING; /CS is
HIGH between valid commands
320
335
360
mA
One Bank Activate Read Precharge Current: tCK= tCK(min); tRC =
tRC(min); CKE = HIGH; 1 bank activated;
IDD1 ^{single read burst with data bus SWITCHING, address and command}
330
345
380
mA
2
inputs are SWITCHING; /CS is High between
valid commands; Iout = 0mA
IDD2P
Precharge Power-Down Current: tCK = tCK(min); all banks idle; CKE =
LOW; all other inputs are HIGH
140
150
160
mA
IDD2N Precharge Standby Current in Non Power-down mode.
190
200
220
mA
IDD3N
Active Standby Current: tCK = tCK(min); 1 bank active; CKE = HIGH;
all other inputs are HIGH
285
300
330
mA
Burst Read Current: tCK = tCK(min); CKE = HIGH; continuous read
IDD4R ^{burst across banks with data bus SWITCHING;}
495
520
550
mA
2
address and command inputs are SWITCHING; Iout = 0 mA
IDD4W
Write Burst Current: tCK = tCK(min); CKE = HIGH; continuous write
burst across banks with data bus SWITCHING;
address and command inputs are SWITCHING
495
520
550
mA
IDD5D ^{Auto Refresh current at tREFI.}
380
400
435
mA
IDD6 Self Refresh Current: CKE = LOW; all other inputs are HIGH
40
40
40
mA
Notes:
1. IDD specifications are tested after the device is properly initialized.
2. Measured with open outputs and ODT off.
3. LOW is defined as inputs stable at VIL(max).
HIGH is defined as inputs stable at VIH(min).
SWITCHING is defined as inputs changing between HIGH and LOW every clock cycle for address and command inputs, and inputs changing with
50% of each data transfer for DQ.
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Publication Release Date: Apr, 22, 2011
Revision A01-002