W641GG2JB Datasheet, PDF (36/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.5 Programmable impedance output drivers and active terminations
6.5.1 GDDR3 IO Driver and Termination
The GDDR3 GRAPHICS SDRAM is equipped with programmable impedance output buffers and active terminations. This allows
the user to match the driver impedance to the system impedance.
To adjust the impedance of DQ[0:31] and RDQS[0:3], an external precision resistor (ZQ) is connected between the ZQ pin and
VSS. The value of the resistor must be six times the value of the desired impedance. For example, a 240 Ω resistor is required for
an output impedance of 40 Ω. The range of ZQ is 210 Ω to 270 Ω, giving an output impedance range of 35 Ω to 45 Ω (one sixth
the value of ZQ within 10%).
The value of ZQ is used to calibrate the internal DQ termination resistors of DQ[0:31], WDQS[0:3] and DM[0:3]. The two termination
values that are selectable using EMRS[3:2] are ZQ / 4 and ZQ / 2.
The value of ZQ is also used to calibrate the internal address command termination resistors. The inputs terminated in this manner
are A[0:11], A[12],CKE#, CS0#, CS1#, RAS#, CAS#, WE#. The two termination values that are selectable upon por up (CKE
latched LOW to HIGH transition of RES) are ZQ / 4 and ZQ / 2.. RES, MF , CLK and CLK# are not internally terminated.
If no resistance is connected to ZQ, an internal default value of 240 Ω will be used. In this case, no calibration will be performed.
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Publication Release Date: Apr, 22, 2011
Revision A01-002