W641GG2JB Datasheet, PDF (33/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

6.4.3.2 Scan Initialization for Stand-Alone mode
VDD
VDDQ
VREF
CLK/
CLK#
SSH
[RES]
SEN
SCK[CS#]
SOE[MF]
SOUT[WDQS]
Pins
Under
Test
Power-up :
VDD / VDDQ / VREF stable
T = 200 us
W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
tSDS tSDH
VALID
tSCS tSCH
tSES
tSCS tSCH
tSCS
tSDS tSDH
VALID
tSCS
ScanOut Bit 0
Boundary Scan Mode
Don‘t care
6.4.4 Scan Initialization in regular SGRAM operation
The Initialization sequence of the boundary scan functionality in regular SGRAM operation has to follow the given sequence.
Sequence Flow:
1. External Voltages (V_DD/V_DDQ/V_REF) need to be stable for 200 μs, RES has to be kept low, external clock has to be stable prior to
RES goes high
2. Bring RES high and keep clock stable for 700tcks, CKE will be latched by rising RES edge, keep t_ATH/t_ATS
3. Bring SEN up to high state to enter boundary scan functionality
4. Operate boundary scan functionality accordingly to the scan features given in Chapter.
5. Boundary scan can be exited by bringing SEN low
6. Wait t_SN for bringing up RES, prior to bringing RES to high state external has to be stable
7. After RES is at high state wait 700tck
8. Continue with regular Initialization sequence (PRE-ALL, EMRS, MRS)
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Publication Release Date: Apr, 22, 2011
Revision A01-002