W641GG2JB Datasheet, PDF (26/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
The WR command is used to initiate a burst write access to an active row. The value on the BA0 - BA2 inputs
selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The row will
remain open for subsequent accesses. For WR commands the value on A8 is set LOW.
WR ^{Input data appearing on the DQs is written to the memory array depending on the value on the DM input}
appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be
written to the memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and
a write will not be executed for that byte / column location.
WR/A
PRE
PREALL
AREF
The WR/A command is used to initiate a burst write access to an active row. The value on the BA0, BA1and
BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The
value on input A8 is set HIGH. The row being accessed will be precharged at the end of the write burst. The
same individual-bank precharge function is performed which is described for the PRE command. Auto
precharge ensures that the precharge is initiated at the earliest valid stage within the burst. The user is not
allowed to issue a new ACT to the same bank until the precharge time (t_RP) is completed. This time is
determined as if an explicit PRE command was issued at the earliest possible time as described in section
―Writes (WR)‖ .
Input data appearing on the DQs is written to the memory array depending on the DM input logic level
appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be
written to the memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and
a write will not be executed to that byte / column location.
The PRE command is used to deactivate the open row in a particular bank. The bank will be available for a
subsequent row access a specified time (t_RP) after the PRE command is issued. Inputs BA0 - BA2 select the
bank to be precharged. A8/AP is set to LOW. Once a bank has been precharged, it is in the idle state and must
be activated again prior to any RD or WR commands being issued to that bank. A PRE command will be treated
as a NOP if there is no open row in that bank, or if the previously open row is already in the process of
precharging.
The PREALL command is used to deactivate all open rows in the memory device. The banks will be available
for a subsequent row access a specified time (t_RP) after the PREALL command is issued. Once the banks have
been precharged, they are in the idle state and must be activated prior to any read or write commands being
issued. The PREALL command will be treated as a NOP for those banks where there is no open row, or if a
previously open row is already in the process of precharging. PREALL is issued by a PRE command with A8/AP
set to HIGH.
The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory content. The
refresh addressing is generated by the internal refresh controller. This makes the address bits ―Don‘t Care‖
during an AREF command. The GDDR3 GRAPHICS SDRAM requires AREF cycles at an average periodic
interval of t_REFI(max). To improve efficiency a maximum number of eight AREF commands can be posted to
one memory device (with t_RFC from AREF to AREF) as described in section ―Auto Refresh Command
(AREF)‖. This means that the maximum absolute interval between any AREF command is 8 x t_REFI(max). This
maximum absolute interval is to allow the GDDR3 Graphics RAM output drivers and internal terminators to
recalibrate, compensating for voltage and temperature changes. All banks must be in the idle state before
issuing the AREF command. They will be simultaneously refreshed and return to the idle state after AREF is
completed. t_RFC is the minimum required time between an AREF command and a following ACT/AREF
command.
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Publication Release Date: Apr, 22, 2011
Revision A01-002