W641GG2JB Datasheet, PDF (7/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
2. FEATURES
• Density: 1Gbit
• Power supply (VDD, VDDQ): 1.8V 0.1V
• Organization: 1 Chip Select x 8 banks x 4M words x 32
bits (1-CS mode) and 2 Chip Select x 8 banks x 2M words
x 32 bits (2-CS mode)
• Eight internal banks per Chip Select for concurrent
operation
• 4n prefetch architecture: 128 bit per array Read or Write
access
• Double-data rate architecture: two data transfers per clock
cycle
• Single ended interface for data, address and command
• Differential clock inputs CLK, CLK#
• Commands entered on each positive CLK edge
• Single ended Read strobe (RDQS) per byte, edge-aligned
with Read data
• Single ended Write strobe (WDQS) per byte, center-
aligned with Write data
• Write data mask (DM) function
• DLL aligns DQ and RDQS transitions with CLK clock
edges for Reads
• Burst length (BL): 4 or 8
• Sequential burst type only
• Programmable CAS latency: 7 to 14
• Programmable Write latency: 3 to 7
• Auto precharge option for each burst access
• Pseudo open drain outputs with 40 pulldown, 40 pullup
• ODT: nom. values of 60 , 120 or 240
• Programmable termination and driver strength offsets
• Refresh cycles: 8192 cycles/32ms
• Auto-refresh and self-refresh modes
• ODT and output drive strength auto-calibration with
external resistor ZQ pin (240 )
• Programmable IO interface including on chip termination
(ODT)
• tRAS lockout support
• Vendor ID for device identification
• Mirror function with MF pin
• Boundary Scan function with SEN pin
• t_WR programmable for Writes with Auto-Precharge
• Calibrated output drive. Active termination support
• Short RAS to CAS timing for Writes
• Operating case temperature range:
Tcase = 0°C to +105°C
• Package: 136-ball TFBGA.
• RoHS Compliant Product
Publication Release Date: Apr, 22, 2011
-7-
Revision A01-002