W641GG2JB Datasheet, PDF (73/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.16.3 Consecutive Read Bursts
6.16.3.1 Gapless Bursts
6.16.3.1.1 Gapless Consecutive Read Bursts
0
1
2
3
6
7
8
9
10
11
12
13
CLK#
CLK
Com. RD
N/D
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr. B/Cx
B/Cy
CAS latency = 5
RDQS
DQ
Dx0 Dx1 Dx2 Dx3 _{Dy0 Dy1} Dy2 Dy3
RDQS
DQ
CAS latency = 6
Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3
B / Cx: Bank / Column address
B / Cy: Bank / Column address
Dx# : Data from B / Cx
Dy# : Data from B / Cy
Com. : Command
Addr. : Address B / C
RD : READ
N/D : NOP or Deselect
Don‘t care
DQs : Terminations off
RDQS : Not driven
Notes :
1. The second RD command may be either for the same bank or another bank.
2. Shown with nominal t_AC and t_DQSQ.
3. Example applies only when READ commands are issued to same device.
4. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS.
5. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data.
- 73 -
Publication Release Date: Apr, 22, 2011
Revision A01-002