W641GG2JB Datasheet, PDF (29/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
6.4.2.1 Internal Block Diagram (Reference only)
DM0
Tie to logic 0
Pins under test
DQ5
D
DQ
CK
D
DQ
CK
1-Gbit GDDR3 Graphics SDRAM
Dedicated Scan D FF
Per signal under test
DQ4
RDQS0
RES (SSH,Scan Shift)
CS# (SCK,Scan Clock)
WDQS0 (SOUT,Scan Out)
SEN, Scn Enable
MF (SOE#, Output Enable)
D
DQ
CK
D
DQ
CK
The following lists the rest of the signals on the scan chain:
DQ[3:0],DQ[31:6],RDQS[3:1],DM[3:1],
CAS#,WE#,CKE,BA[2:0],A[11:0],CK, CK# and ZQ
Two RFU‘s (J-2 and J-3 on 136-ball package) will be on
The scan chain and will read as a logic ―0‖
The following lists the signals not on the scan chain:
VDD,VSS,VDDQ,VSSQ,VDDA,VSSA and VREF
Puts device into scan mode and re-maps pins to scan functionality
6.4.2.2 Boundary Scan Exit Order
BIT# BALL BIT#
1
D-3
13
2
C-2
14
3
C-3
15
4
B-2
16
5
B-3
17
6
A-4
18
7
B-10
19
8
B-11
20
9
C-10
21
10
C-11
22
11
D-10
23
12
D-11
24
BALL
E-10
F-10
E-11
G-10
F-11
G-9
H-9
H-10
H-11
J-11
J-10
L-9
BIT#
25
26
27
28
29
30
31
32
33
34
35
36
BALL
K-11
K-10
K-9
M-9
M-11
L-10
N-11
M-10
N-10
P-11
P-10
R-11
BIT#
37
38
39
40
41
42
43
44
45
46
47
48
BALL
R-10
T-11
T-10
T-3
T-2
R-3
R-2
P-3
P-2
N-3
M-3
N-2
BIT#
49
50
51
52
53
54
55
56
57
58
59
60
BALL
L-3
M-2
M-4
K-4
K-3
K-2
L-4
J-3
J-2
H-2
H-3
H-4
BIT#
61
62
63
64
65
66
67
BALL
G-4
F-4
F-2
G-3
E-2
F-3
E-3
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Publication Release Date: Apr, 22, 2011
Revision A01-002